The present invention relates to a memory control device and a semiconductor processing apparatus and, more particularly, relates to a memory control device and a semiconductor processing apparatus for controlling a semiconductor memory by using a series of commands.
Hitherto, an image processing apparatus for compressing/decompressing an image is provided with an SDRAM (Synchronous Dynamic Random Access Memory) for storing a large amount of data, and an SDRAM controller for controlling the SDRAM (refer to, for example, Japanese Unexamined Patent Publication No. 2000-10856).
In the control of the SDRAM, for initialization at the time of power-on, a change in the drive frequency, return to a normal mode from a low-power mode, calibration, or the like, a command issuing sequence for issuing a series of SDRAM commands at sufficient intervals has to be execute. As a limitation of the command intervals, usually, only the minimum value is specified. Concrete length of the minimum interval varies from a few cycles to hundreds of microseconds (tens of thousands of cycles).
As a first method of executing the command issuing sequence, the SDRAM controller is provided with a controller as dedicated hardware (state machine) and the sequence is automatically executed by the controller.
As a second method of executing the command issuing sequence, an instruction to issue an SDRAM command is given from an external controller to the SDRAM controller to make the SDRAM controller issue an SDRAM command. In the second method, by repeatedly giving the command issue instruction from the external controller, the command issuing sequence is executed.